1 standard products ut54acs165/UT54ACTS165 8-bit parallel shift registers datasheet november 2010 www.aeroflex.com/logic features ? complementary outputs ? direct overridin g load (data) inputs ? gated clock inputs ? parallel-to-serial data conversions ? 1.2 cmos - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 16-pin dip - 16-lead flatpack ? ut54acs165 - smd 5962-96558 ? UT54ACTS165 - smd 5962-96559 description the ut54acs165 and the ut54acts1 65 are 8-bit serial shift regis- ters that, when clocked, shift the data toward serial output q h . parallel- in access to each stage is provided by eight individual data inputs that are enabled by a low level at the sh/ld input. the devices feature a clock inhibit function and a co mplemented serial output q h . clocking is accomplished by a low-to-high transition of the clk input while sh/ld is held high and clk inh is held low. the functions of the clk and clk inh (clock inhibit) inputs are interchangeable. since a low clk input and a low-to-high transition of clk inh will also accomplish clocking, cl k inh should be changed to the high level only while the clk input is high. pa rallel loading is disabled when sh/ld is held high. parallel inputs to the registers are enabled while sh/ld is low independently of the le vels of clk, clk inh or ser inputs. the devices are characterized over full military temperature range of -55 c to +125 c. function table note: 1. q n = the state of the referenced output one setup time prior to the low-to- high clock transition.pinouts pinouts 16-pin dip top view 16-lead flatpack top view logic symbol inputs internal outputs outputs sh/ ld clk inh clk ser parallel a . . . h q a q b q h q h l x x x a . . . h a b h h h l l x x q a q b q h q h h l h x h q a q g q g h l l x l q a q g q g h h x x x q a q b q h q h 1 2 3 4 5 7 6 16 15 14 13 12 10 11 sh/ld clk e f g h q h v dd clk inh d c b a ser 8 9 v ss q h 1 2 3 4 5 7 6 16 15 14 13 12 10 11 v dd 89 sh/ld clk e f g h q h clk inh d c b a ser v ss q h (1) sh/ld (15) clk inh c2/ c1 (load) note: 1. logic symbol in accordance with ansi/ieee std 91-1984 and iec publication 617-12. (10) ser (11) a srg8 (9) q h (7) q h 1 (2) clk 2d 1d (12) b (13) c (14) d (3) e (4) f (5) g (6) h 1d 1d
2 logic diagram abcdef g h (11 ) (12) (13) (14) (4) (5) (6) (3) s c d r (1) (15) (2) (10 ) clk inh clk ser q c q d q e q f q g sh/ld (9) (7) q h q h s c d r s c d r s c d r s c d r s c d r s c d r q a s c d r q h q b
3 operational environment 1 notes: 1. logic will not latchup during radiation expo sure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maxi mum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the opera tional sections is not recommend ed. exposure to absolute maxi mum rating conditio ns for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
4 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c); unless otherwise noted, tc is per the temperature range ordered. symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 2.9 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 ? = 1mhz @ 0v 15 pf c out output capacitance 5 ? = 1mhz @ 0v 15 pf
5 notes: 1. functional tests are conducted in accordance with mil-std-883 with the followi ng input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any inpu t voltage within the above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit bu t not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capac itance (per output buff er) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualifi cation and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
6 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c); unless otherwise noted, tc is per the temperature range ordered. notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). 3. based on characterization, hold time (t h3 ) of 0ns for data pins a-h, can be assumed if data setup time (t su2 ) is > 10ns. this is guaranteed, but not tested. symbol parameter minimum maximum unit t phl clk or clk inh to q h or q h 2 21 ns t plh clk or clk inh to q h or q h 2 18 ns t phl sh/ld to q h or q h 2 21 ns t plh sh/ld to q h or q h 2 18 ns t phl h to q h 2 21 ns t plh h to q h 2 17 ns t phl h to q h 2 20 ns t plh h to q h 2 18 ns f max maximum clock frequency 71 mhz t su1 ser, sh/ld , clkinh or clk setup time before clk or clk inh 7 ns t su2 data setup time before sh/ld 7 ns t h1 ser hold time after clk or clk inh 2 ns t h2 clk inh hold time after clk 2 ns t h3 3 hold time for any input after sh/ld 2 ns t w minimum pulse width clk or clk inh high clk or clk inh low sh/ld 7 ns
7 packaging side-brazed packages
8 flatpack packages
9 ut54acs165/UT54ACTS165: smd 5962 ***** ** * * * * lead finish: (notes 1 & 2) a = solder c = gold x = optional package type: x = 16-lead ceramic botto m-brazed dual-in-line flatpack c = 16-lead ceramic side-brazed dip class designator: q = qml class q v = qml class v device type: 01 drawing number : 96558 = ut54acs165 96559 = UT54ACTS165 total dose: (notes 3 & 4) r = 1e5 rads(si) f = 3e5 rads(si) g = 5e5 rads(si) h = 1e6 rads(si) notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, pa rt marking will match the lead finish and w ill be either ?a? (solder) or ?c? (gold). 3. total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening. for protot ype inquiries, contact factory. 4. device type 02 is only offered with a tid tolerance guarantee of 3e5 rads(si) or 1e6 rads(si) and is tested in accordance wi th mil-std-883 test method 1019 condition a and section 3.11.2 . device type 03 is only offered with a tid tolerance guarantee of 1e5 rads(si), 3e5 rads(si) , and 5e5 rads(si), and is tested in accordance with mil-std-883 test method 1019 condition a.
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